1. Field of the Invention
This invention relates to the design of integrated circuits; and, in particular, relates to the design of input buffers in integrated circuits.
2. Discussion of the Related Art
In most integrated circuits, logic or boolean states are encoded by voltage levels. For example, in integrated circuits using "positive logic" TTL levels, the logic "true" (i.e. boolean "1" or "high") state is represented in a signal by a voltage level above 2.2 volts, and the logic "false" (i.e. boolean "0" or "low") state is represented in a signal by a voltage level below 0.7 volts. Clearly, a logic circuit must correctly receive the logic states of its input signals to correctly and reliably operate.
An integrated circuit receives its input signals through input buffer circuits. An example of a typical complementary metal-oxide-semiconductor (CMOS) input buffer circuit is shown in FIG. 1. As shown in FIG. 1, an input buffer 100 is formed by a CMOS invertor comprising PMOS transistor 101, and NMOS transistor 102. The input signal is received on lead 103 and an output signal opposite in logic state to the input signal is provided on lead 104. The output signal is often buffered to be distributed to the rest of the integrated circuit.
In input buffer 100, when the voltage level of the Signal on input lead 103 exceeds a "threshold voltage", the output signal on lead 104 is pulled to logic low by NMOS transistor 102. Conversely, when the voltage level of the signal on input lead 103 falls below the threshold voltage, the output signal on lead 104 is pulled to logic high by PMOS transistor 101. This threshold voltage is determined by the supply voltage and the relative sizes of transistors 101 and 102. For example, in one implementation in which the supply voltage is 5 volts relative to ground, using a size ratio of 1:5 between PMOS transistor 101 and NMOS transistor 102, a 1.5 volt threshold voltage is achieved for the input buffer 100.
Input buffer 100 of FIG. 1 has a severe drawback in that the threshold voltage achieved is susceptible to variation due to changes in the operating environment (e.g. power supply and temperature variations) or fabrication conditions (e.g. input buffer 100's electrical characteristics). In particular, input buffer 100 is especially susceptible to "ground bounce", which is a momentary surge of the local "ground" voltage of the integrated circuit due to a large current being sunk momentarily by the integrated circuit. Under such condition, the threshold voltage of input buffer 100 may rise by as much as the ground bounce. Since the external input signal does not follow the ground bounce, this sudden surge in the threshold voltage may result in a logic high value in the input signal on input lead 103 being incorrectly received as a logic low value, thereby causing an undesirable result.
As mentioned above, other changes in operational and fabrication conditions can also affect the threshold voltage to result in incorrect operation of the integrated circuit. For example, process variations in a CMOS process can affect the PMOS and NMOS transistors differently so as to result in a threshold voltage deviated from its intended value. Temperature variations too can affect the PMOS and NMOS transistors disparately to result in a shift in threshold voltage from its intended threshold voltage. Further, in input buffer 100, variations in the supply voltage V.sub.cc can also cause a shift in the threshold voltage from its intended value, thereby affecting the speed of the input buffer.
Thus, an input buffer which maintains a substantially constant threshold voltage under changes in operational and fabrication conditions is highly desirable.